ELR106 - LOGIC DESIGN ENGINEER (STA)
ELR106 - LOGIC DESIGN ENGINEER (STA)
Manufacturing
Middle/Senior
Ho Chi Minh City
Full-time
Responsibilities
Netlist qualification
Perform LSI ChipTop netlist checking as our design rule such as DFTcheck (Design For Test), HLDRC ( Highperformance Logic Design Rule Checker), STAcheck (Static Timing Analysis), FalseCheck, FV (logic equivalent check).
Monitor and control error judgment progress.
Manage input/output design data b/t Front End vs. Middle End and Back End.
Perform Logic ECO, and DFT in RTL, synthesis, and tessent DRC at the Hierarchical level.
Perform CT (combine test) Environment building.
SDC management for each milestone
Hierarchical SDC creation.
IP level constraint integration.
Delivery of data to other design teams with high quality.
Support SDC debugging for project members.
Monitor and control GCA (Galaxy constraint analysis) and PTE (PrimeTime error) judgment progress.
ECO timing.
Work with other design teams (DFT, STA, Layout) to develop schedules and solve problems for timing closure until TapeOut.
Requirements
Master's or Bachelor's degree in Electrical or Computer Engineering.
At least 4 years of experience in the related role.
Ability to Conduct/schematic analysis for debugging.
STA (Static Timing Analysis) experience.
Experience in Design Compile, Fusion, Genus, Conformal-lec, PrimeTime tool, VCS, Xcelium.
Experience in scripting languages such as C-Shell, Perl, Tcl, Visual Basic, Python, Jason, Ruby, and Java.
Good at management by Ms.Office tools such as Excel skills.
Good communication skills as well as problem-solving skills.
Ability to work under pressure and multitask.
Good English communication skills.
*** Nice to have: Experience in Spyglass CDC, RTL-A; CT environment building
Benefits
Working location: Probation in District 7, HCM, then Remote Full-time
Salary range: Based on current salary
Infomation
Offered Salary
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Skills